Embedded systems used in real-time applications require low power, less area and high computation\nspeed. For digital signal processing, image processing and communication applications, data\nare often received at a continuously high rate. The type of necessary arithmetic functions and matrix\noperations may vary greatly among different applications. The RTL-based design and verification\nof one or more of these functions could be time-consuming. Some High Level Synthesis tools\nreduce this design and verification time but may not be optimal or suitable for low power applications.\nThe design tool proposed in this paper can improve the design time and reduce the verification\nprocess. The design tool offers a fast design and verification platform for important matrix\noperations. These operations range from simple addition to more complex matrix operations such\nas LU and QR factorizations. The proposed platform can improve design time by reducing verification\ncycle. This tool generates Verilog code and its testbench that can be realized in FPGA and VLSI\nsystems. The designed system uses MATLAB-based verification and reporting.
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